1. Field of the Invention
The present invention relates to a monitor circuit and relates, in particular, to technology of controlling a resource (such as a power supply voltage and a clock frequency, for example) with a monitor circuit to reduce power consumption.
2. Description of Related Art
Scaling down a semiconductor integrated circuit and increasing its integration level may increase the power consumption. The increase of the power consumption in the semiconductor integrated circuit may increase a temperature of the semiconductor integrated circuit. The increase of the temperature may decrease the life of elements of the semiconductor integrated circuit. The decrease in the life of the elements leads to a decreasing reliability of an apparatus including the semiconductor integrated circuit. The increase of the power consumption of the semiconductor integrated circuit may impose a problem that the required power may approach the limit of a power supply facility owned by a customer. Therefore, there may be a need for reducing the power consumption in the semiconductor integrated circuit.
As a technique for reducing the LSI power consumption, technology of halting or delaying a logic circuit which does not need to operate, such as a clock gating or a data gating, is known. However, as a speed and performance is increased in an LSI (Large Scale Integrated circuit), such techniques may not restrain the increasing power consumption when the clock frequency is increased or a multicore is adopted in the processor.
FIGS. 1 and 2 are block diagrams illustrating circuits of a related art for restraining the increasing power consumption. The circuits shown in FIG. 1 are configured based on DVFS (Dynamic Voltage Frequency Scaling) to monitor a power supply drop and a temperature change, and adjust the power supply voltage and the frequency of the LSI. The operation of the LSI is changed dynamically and flexibly so that the monitored power supply drop and temperature change do not reach a limit amount. Thereby, the power consumption does not exceed a critical value.
Performance monitors are arranged in a circuit shown in FIG. 2. Based on the performance monitors, the system is controlled corresponding to a performance monitored by the performance monitors. The performance monitors monitor the performance by checking whether FFs (Flip Flops) mutually latch a correct data.
As technology for monitoring a delay time of a semiconductor integrated circuit, for example, technology disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 61-041976) is known. FIG. 3 is a circuit diagram illustrating a ring oscillator circuit disclosed in Patent Document 1. The technology disclosed in Patent Document 1 includes a ring oscillator and a measurement circuit for measuring an oscillation frequency of the ring oscillator. The circuit shown in FIG. 3 monitors the delay time by inspecting effective bits obtained by the measurement circuit. Besides the above described technology, technology for reducing the power consumption of the semiconductor integrated circuit is known (see, for example, Patent Documents 2 to 5).    [Patent Document 1] Japanese Patent Laid-Open No. 61-041976    [Patent Document 2] Japanese Patent Laid-Open No. 2005-073494    [Patent Document 3] Japanese Patent Laid-Open No. 01-197673    [Patent Document 4] Japanese Patent Laid-Open No. 06-118122    [Patent Document 5] Japanese Patent Laid-Open No. 07-020204